For recent high speed semiconductor memory devices, specifically, synchronous memories, their cycle time tends to be determined by not their read cycle time but their write cycle time, since the write operation should be completed in a short write cycle and the margin between cell select signals and a write pulse signal should be assured.
FIG. 1 illustrates a prior art semiconductor memory device. Reference numeral 100 represents an array of memory cells, 110 a bit line load and equalizing circuit formed by bit line load transistors 1 and 2 and a bit line equalizing transistor 3, 120 a sense amplifier, 130 a data output buffer, 140 a data input buffer, 150 a write driver, and 160 a column pass gate circuit formed by column pass gate transistors 4A, 5A, 4B and 5B.
Also, reference symbol WL1, WL2, . . . , WLn designate word lines, BL and BL (The BL represents an inverted BL) an a pair of bit lines, and DL and DL (The DL represents an inverted DL) a pair of data lines.
In the prior art semiconductor memory device, when a pulse signal PWR (i.e, write recovery control signal) is activated, the bit lines BL and BL both are precharged to a predetermined voltage level.
In such a pecharge state, if one of the word lines WL1 to WLn is selected by a row select signal (not shown), further, if column select signals Yi and Yi (The Yi represents an inverted Yi) and a write pulse signal PWB (not shown) are activated, then one of the data lines DL and DL is pulled down to a low level (usually, ground voltage) by the write driver 150 such that a corresponding bit line BL or BL is also pulled down to the low voltage level by means of charge sharing with the corresponding data line DL or DL via the column gate circuit 160. At this time, the other bit line is pulled up to a high voltage level (usually, power supply voltage). In this manner, a data is written into a memory cell.
By the write recovery control signal PWR, the memory device is made to be ready for the next write cycle such that the bit lines BL and BL both are brought back into the precharge state again.
As reduced is the write cycle time, however, the width of the write pulse signal PWB has also to be shorten on account of inter-cycle margin, resulting in the imperfection in writing a data into a memory cell since the write operation has been completed before a pertinent bit line is sufficiently pulled down to a low voltage level, thereby increasing the possibility of a malfunction of the memory device so as to prevent the high speed write operation.